1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and particularly, to a semiconductor device including a MOS transistor and method of manufacturing the same.
2. Description of the Background Art
The allowable value to alignment mismatch (alignment margin) of the constructions in manufacturing steps is decreased as semiconductor devices are miniaturized. This is an obstacle to high integration of semiconductor devices. In order to facilitate integration without being restricted by the alignment margin, it has been examined that the semiconductor elements constituting a semiconductor device are made to have such a structure as may not be subject to disadvantages in the event of an alignment mismatch.
For example, there is such a method of making a MOS transistor have a self align contact structure (hereinafter referred to as SAC structure) in a memory part where high integration is especially required in semiconductor devices.
FIG. 31 gives an one example of SAC structure. In FIG. 31, two gates GT are disposed a predetermined distance apart on a silicon substrate 101. The gates GT comprise a gate oxide film 102 disposed on the silicon substrate 101, a gate electrode 103 on the gate oxide film 102, an upper nitride film 104 on the gate electrode 103, and a sidewall nitride film 105 disposed such as to make contact with the side faces of the upper nitride film 104, gate electrode 103 and gate oxide film 102. A source/drain layer SD is disposed in the surface of the silicon substrate 101 lying on both sides of the gate GT.
An interlayer insulating film IZ formed from a silicon oxide film is disposed such as to cover the two gates GT, and a contact hole CH penetrating the interlayer insulating film IZ is disposed such as to reach the source/drain layer SD between the gates GT. A conductor layer CL is buried in the contact hole CH.
Since the gate electrode 103 is covered with the upper nitride film 104 and sidewall nitride film 105, it is possible to prevent the upper nitride film 104 and sidewall nitride film 105 from being removed in forming the contact hole CH. In the event of a contact hole dislocation, it is possible to prevent the gate electrode 103 from being exposed, and no short-circuit is developed between the conductor layer CL and gate electrode 103. Thereby, the contact hole CH can be formed without being restricted by the alignment margin. In this case, the opening size of the contact hole CH is determined in a self-aligned manner by the distance between the gates GT, and hence it can be called xe2x80x9cself align contact.xe2x80x9d
Accordingly, the employment of the SAC structure allows it to be less subject to the restriction of alignment margin, and thus facilitates integration. Therefore, the SAC structure is useful with the memory part in which the distance between the two gates is progressively shorter. Unfortunately, the SAC structure is not applicable to the logic part.
Specifically, in the logic part, the resistance value is lowered for attaining high speed operation by salicide structure that a silicide layer is formed in a self-aligned manner on a gate electrode and on a source/drain layer of a MOS transistor. Whereas in the SAC structure, an upper nitride film is formed on a gate electrode, and it is impossible to form a silicide layer on the gate electrode, thus failing to form a MOS transistor of SAC structure in the logic part.
Conventionally, such a method of forming a silicide protection film comprised of a silicon oxide film has been employed in order to prevent that a silicide layer is formed on a gate electrode of a protection circuit for the protection of a main circuit from surge voltage, and on a source/drain layer in the vicinity of the gate electrode, thereby avoiding the current concentration due to irregularities of the crystal particles in the silicide layer.
FIG. 32 gives an example of formation of a silicide protection film. As shown in FIG. 32, gates GT1 and GT2 are disposed a predetermined distance apart on a silicon substrate SB.
The gate GT1 comprises a gate oxide film OX disposed on the silicon substrate SB, a gate electrode GE on the gate oxide film OX, and a sidewall oxide film SW disposed such as to make contact with the side faces of the gate electrode GE and gate oxide film OX.
The gate GT2 comprises a gate oxide film OX disposed on the silicon substrate SB, a gate electrode GE on the gate oxide film OX, a silicide layer SF on the gate electrode, and a sidewall oxide film SW disposed such as to make contact with the side faces of the gate electrode GE, silicide layer SF and gate oxide film OX.
A source/drain layer SD is formed in the surface of the silicon substrate SB lying on both sides of the gates GT1 and GT2, and a silicide layer SF is disposed on the source/drain layer SD.
Note that a silicide protection film SP is formed on the gate GT1 and on the surface of the source/drain layer SD lying in the vicinity of the gate GT1, and no silicide layer SF is disposed on the gate GT1 and on the surface of the source/drain layer SD in the vicinity of the gate GT1.
In this manner, it is avoidable that a silicide layer is formed on the gate GT1 and on the source/drain layer SD in the vicinity of the gate GT1, by virtue of the presence of silicide protection film SP. It is not impossible, therefore, that a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together. However, the manufacturing steps is complicated by selective formation of a silicide protection film SP, and restriction is imposed on the distance between the gates, because of the necessity of forming the silicide protection film SP. Consequently, hitherto no attempts have been made to construct so that a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together in both memory part and logic part. This is true for circuit parts other than the memory part and logic part.
To meet demanding requirements of high integration and high speed operation of semiconductor devices in recent years, the inventors recognized the necessity of a technique of providing together a MOS transistor of SAC structure and a MOS transistor of salicide structure when they attained such a technical thought of employing a MOS transistor of salicide structure in a memory part and a MOS transistor of SAC structure in a logic part.
According to a first aspect of the invention, a semiconductor device having a plurality of circuit parts that are of different constructions and disposed on a semiconductor substrate, each of the circuit parts comprises: at least one first and second gate structures disposed on at least either of the semiconductor substrate and an isolation insulating film disposed on the semiconductor substrate; an interlayer insulating film covering the first and second gate structures; and a plurality of contacts penetrating the interlayer insulating film and reaching at least either of the semiconductor substrate and the isolation insulating film, the at least one first gate structure comprising: a first gate oxide film; a first gate electrode disposed on the first gate oxide film; an upper insulating film disposed on the first gate electrode; and a first sidewall insulating film disposed on side faces of the upper insulating film, the first gate electrode and the first gate oxide film, and the at least one second gate structure comprising: a second gate oxide film; a second gate electrode disposed on the second gate oxide film; a silicide layer disposed on the second gate electrode; and a second sidewall insulating film disposed on side faces of the silicide layer, the second gate electrode and the second gate oxide film.
According to a second aspect of the present invention, the at least one first gate structure is a plurality of first gate structures; and the plurality of contacts have a self align contact with which the opening size of the contact hole is determined in a self aligned manner by the distance between the plurality of first gate structures, the self align contact having a contact hole penetrating the interlayer insulating film and reaching the semiconductor substrate, and being disposed between the plurality of first gate structures in parallel arrangement.
According to a third aspect of the present invention, the plurality of contacts are provided with a shared contact having a contact hole penetrating the interlayer insulating film and reaching the semiconductor substrate and the silicide layer of the at least one second gate structure, the contact hole being disposed between the at least one first and second gate structures in parallel arrangement.
According to a fourth aspect of the present invention, the at least one second gate structure is a plurality of second gate structures; and the plurality of contacts are provided with a shared contact having a contact hole disposed between the plurality of second gate structures in parallel arrangement, the contact hole penetrating the interlayer insulating film, and reaching the semiconductor substrate and the silicide layer of at least either of the plurality of second gate structures.
According to a fifth aspect of the present invention, the at least one second gate structure for engagement with the contact hole is disposed on the isolation insulating film.
According to a sixth aspect of the present invention, the at least one first and second gate structures are provided together on the semiconductor substrate, having sandwiched therebetween the isolation insulating film; the semiconductor substrate surfaces on both sides of the at least one first and second gate structures have a source/drain layer; and the plurality of contacts are provided with a shared contact having a contact hole disposed between the at least one first and second gate structures, the contact hole penetrating the interlayer insulating film, reaching the source/drain layers having sandwiched therebetween the isolation insulating film, and the isolation insulating film, and reaching the silicide layer of the at least one second gate structure.
According to a seventh aspect of the present invention, a central gate structure that corresponds to the at least one first gate structure and is disposed such as to locate at a relatively center; and first side and second side gate structures that correspond to either of the at least one first and second gate structures, and are disposed on both sides of the central gate structure, and characterized in that the plurality of contacts have a contact hole disposed between the first and second side gate structures such as to expose the central gate structure, the contact hole penetrating the interlayer insulating film and reaching at least either of the semiconductor substrate and the isolation insulating film, and have a conductor layer being buried in the contact hole and covering the central gate structure.
According to an eighth aspect of the present invention, the central gate structure and the first and second side gate structures are disposed on the isolation insulating film; the first and second side gate structures correspond to the at least one second gate structure; and the contact hole is disposed such as to reach the silicide layer of the first and second side gate structures.
According to a ninth aspect of the present invention, the central gate structure is disposed on the isolation insulating film; the first and second side gate structures are disposed on the semiconductor substrate, having sandwiched therebetween the isolation insulating film; the semiconductor substrate surfaces on both sides of the first and second side gate structure have a source/drain layer, respectively; and the contact hole is disposed such as to reach the source/drain layers having sandwiched therebetween the isolation insulating film of the first and second side gate structures.
According to a tenth aspect of the present invention, the central gate structure and the first side gate structure are disposed on the isolation insulating film, and the first side gate structure corresponds to the at least one second gate structure; the second side gate structure is disposed on the semiconductor substrate; the semiconductor substrate surfaces on both sides of the second side gate structure have a source/drain layer; and the contact hole is disposed such as to reach the source/drain layer on the isolation insulting layer side of the second side gate structure and reach the silicide layer of the first side gate structure.
According to an eleventh aspect of the present invention, the central gate structure is disposed on the isolation insulating film; the first and second side gate structures are disposed on the semiconductor substrate, having sandwiched therebetween the isolation insulating film; the semiconductor substrate surfaces on both sides of the first and second side gate structures have a source/drain layer, respectively; the first and second side gate structures correspond to the at least one second gate structure; and the contact hole is disposed such as to reach the source/drain layers having sandwiched therebetween the isolation insulating film of the first and second side gate structures, and also reach the silicide layers of the first and second side gate structures.
According to a twelfth aspect of the present invention, the at least one second gate structure is a plurality of second gate structures; the semiconductor substrate surfaces on both sides of the plurality of first gate structures have a source/drain layer; the plurality of first gate structures are disposed in a region in the vicinity of the self align contact; and the plurality of second gate structures are continuous with the plurality of first gate structures on other regions than the region in the vicinity of the self align contact.
According to a thirteenth aspect of the present invention, the gate electrode of the plurality of first gate structures has an impurity of the same conductivity type as that of the source/drain layer.
According to a fourteenth aspect of the present invention, the semiconductor substrate surfaces on both sides of the plurality of first gate structures have a source/drain layer, respectively; and a plane array pattern of the contact hole is set such that the source/drain layers adjacent each other are of different patterns.
According to a fifteenth aspect of the present invention, the semiconductor device further comprises a silicide layer on an upper part of the source/drain layer.
According to a sixteenth aspect of the present invention, a method of manufacturing a semiconductor device which has a plurality of circuit parts that are of different constructions and disposed on a semiconductor substrate, each of the circuit parts having first and second gate structures which are disposed on at least either of the semiconductor substrate and an isolation insulating film on the semiconductor substrate, comprises the steps of: (a) forming an oxide film on the semiconductor substrate; (b) forming a gate electrode layer on the oxide film; (c) selectively forming a nitride film on the gate electrode layer such as to correspond to the location of the first gate structure; (d) selectively forming a mask made of oxide film on the nitride film and on the gate electrode layer such as to correspond to the location of the second gate structure; (e) by using the mask, etching away the nitride film and the gate electrode layer, and selectively removing the mask and the oxide film, so that a first gate oxide film, a first gate electrode on the first gate oxide film and an upper nitride film on the first gate electrode are formed such as to correspond to the location of the first gate structure, and that a second gate oxide film and a second gate electrode on the second gate oxide film are formed such as to correspond to the location of the second gate structure; (f) forming a first sidewall nitride film on side faces of the upper nitride film, the first gate electrode and the first gate oxide film, to form the first gate structure, and forming a second sidewall nitride film on side faces of the second gate electrode and the second gate oxide film; and (g) forming a silicide layer on an upper part of the second gate electrode, to form the second gate structure.
According to a seventeenth aspect of the present invention, the method of manufacturing a semiconductor device further comprises the step, prior to the step (g), of forming a source/drain layer in the surface of the semiconductor substrate, and characterized in that the step (g) includes a salicide step of forming a silicide layer on the source/drain layer at the same time.
With the first aspect, in a semiconductor device having a plurality of circuit parts of different constructions, such as a memory part (e.g., SRAM) and a logic part, high integration and high speed operation are attainable by providing together the self align contact structure based on the first gate structure and the salicide structure based on the second gate structure, in the memory part. In addition, high integration is also attainable while maintaining high speed operation, by disposing the mentioned self align contact and salicide structure in the logic part.
With the second aspect, the self align contact structure is obtainable based on the first gate structures in parallel arrangement, and the distance between the gates can be reduced for achieving high integration.
With the third aspect, a shared contact can be constructed based on the second gate structure, thereby simplifying the construction for the connection between the silicide layer of the second gate structure, i.e., the gate electrode, and the semiconductor substrate, i.e., the active region.
With the fourth aspect, a shared contact can be constructed based on either of the second gate structures in parallel arrangement, thereby simplifying the construction for the connection between the silicide layer of the second gate structure, i.e., the gate electrode, and the semiconductor substrate, i.e., the active region.
With the fifth aspect, the resistance of the second gate structure can be lowered by disposing a silicide layer in the second gate structure lying on the isolation insulating layer serving as a gate wiring.
With the sixth aspect, it is possible to simplify the construction for electrically connecting the electrically isolated source/drain layers having sandwiched therebetween the isolation insulating film, to the silicide layer, i.e., the gate electrode, of the second gate structure.
With the seventh aspect, although the conductor layer covers the central gate structure, the gate electrode of the first gate structure is covered with the insulating film, and thus it can exist electrically independently of the first and second side gate structures. This increases the degree of freedom of layout, leading to high integration.
With the eighth aspect, even when wirings desired to be electrically isolated from each other are present between wirings desired to be electrically connected with each other, a connection between the latter wirings can be made easily by covering the former wirings with an insulating film and disposing a conductor layer such as to cover the insulating film. This structure realizes simplification of manufacturing steps and increase in the degree of freedom of layout, leading to high integration. Whereas in the conventional construction, a single contact is provided on wirings desired to be electrically connected with each other, and a connection between the contacts is made through a wiring layer disposed on an interlayer insulating film. As a result, the manufacturing steps is complicated, and there are many limitations upon layout.
With the ninth aspect, even when wirings desired to be electrically isolated from each other are present between source/drain layers desired to be electrically connected with each other, which layers having sandwiched therebetween an isolation insulating film, a connection between the source/drain layers can be made easily by covering the wirings (desired to be electrically isolated) with an insulating film and disposing a conductor layer such as to cover the insulating film. This simplifies manufacturing steps and increases the degree of freedom of layout, leading to high integration. Whereas in the conventional construction, a single contact is provided on source/drain layers desired to be electrically connected with each other, and a connection between the contacts is made through a wiring layer disposed on an interlayer insulating film. As a result, the manufacturing steps is complicated, and there are many limitations upon layout.
With the tenth aspect, even when wirings desired to be electrically isolated from each other are present between a wiring and source/drain layer which are desired to be electrically connected with each other, a connection between the latter wiring and source/drain layer can be made easily by covering the former wirings (desired to be electrically isolated) with an insulating film and disposing a conductor layer such as to cover the insulating film. This simplifies manufacturing steps and increases the degree of freedom of layout, leading to high integration. Whereas in the conventional construction, a single contact is provided on a wiring and source/drain layer which are desired to be electrically connected with each other, and a connection between the contacts is made through a wiring layer disposed on an interlayer insulating film. As a result, the manufacturing steps is complicated, and there are many limitations upon layout.
With the eleventh aspect, even when wirings desired to be electrically isolated from each other are present between two MOS transistors for which it is desired to electrically connect between their respective source/drain layers and between their respective gate electrodes, a connection between the source/drain layers and a connection between the gate electrodes can be made easily by covering the wirings (desired to be electrically isolated) with an insulating film and disposing a conductor layer such as to cover the insulating film. This simplifies manufacturing steps and increases the degree of freedom of layout, leading to high integration. Whereas in the conventional construction, a single contact is provided on a wiring and source/drain layer which are desired to be electrically connected with each other, and a connection between the contacts is made through a wiring layer disposed on an interlayer insulating film. As a result, the manufacturing steps is complicated, and there are many limitations upon layout.
With the twelfth aspect, a low-resistance of the gate electrode is achievable, and high integration is attainable while maintaining high speed operation, by limiting the location of the self align contact structure formed from the first gate structures in parallel arrangement, only in the vicinity of the self align contact, and disposing the second gate structure, i.e., the gate having the silicide layer, such as to be continuous with the first gate structures in parallel arrangement, in other regions than the region in the vicinity of the self align contact.
With the thirteenth aspect, when the first gate structure is a dual polysilicon gate, even in the construction of connecting MOS transistors of different conductive types, it is possible to prevent a parasitic diode from being formed in the junction between two gates into which impurities of different conductivity types have been implanted, by disposing the second gate structure, i.e., the gate having the silicide layer, such as to be continuous with the first gate structures in parallel arrangement, in other regions than the region in the vicinity of the self align contact.
With the fourteenth aspect, by setting a plane array pattern of contact holes when employing the self align contact structure, such that the source/drain layers adjacent each other are of different patterns, the localization of the contact holes is lowered to lessen the possibility of disadvantages in pattern resolution due to proximity effect and the like, when a resist patterning is performed by using photolithography technique in the formation of contact holes. This permits a further reduction in the distance between the gates.
With the fifteenth aspect, the contact resistance between the source/drain layer and contact part can be lowered by overlaying a silicide layer on the source/drain layer.
With the sixteenth aspect, a gate where no silicide layer will be formed can be selectively formed on a desired location in a relatively easy step, by previously and selectively forming a nitride film that serves as an upper nitride film for the prevention of any silicide layer formation, on a gate electrode layer, and then forming a mask made of an oxide film on the nitride film.
With the seventeenth aspect, a silicide layer can be also formed on the source/drain layer at the same time, making it easy to obtain the construction with a low contact resistance between the source/drain layer and contact part.
An object of the present invention is to provide a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.